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Woo! Got my clock module down to two chips total (plus resistors, capacitors, and such).

Really basic stuff, but I'm still learning #KiCad.

#kicad

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in reply to Jonathan Lamothe

Jonathan Lamothe
Jonathan Lamothe
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Just realized the the current design won't honour the halt signal when it's in manual pulse mode... 🙁
in reply to Jonathan Lamothe

Jonathan Lamothe
Jonathan Lamothe
•
Aha! A hacky solution, but I can fix it by wiring the switch that sends the manual clock pulse to ~HLT instead of +5V. No additional logic gates required.

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